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MICRF506
410MHz and 450MHz ISM Band Transceiver
General Description
The MICRF506 is a true single-chip, frequency shift keying (FSK) transceiver intended for use in half-duplex, bidirectional RF links. The multi-channeled FSK transceiver is intended for UHF radio equipment in compliance with the European Telecommunication Standard Institute (ETSI) specification, EN300 220. The transmitter consists of a PLL frequency synthesizer and power amplifier. The frequency synthesizer consists of a voltage-controlled oscillator (VCO), a crystal oscillator, dual modulus prescaler, programmable frequency dividers, and a phase-detector. The loop-filter is external for flexibility and can be a simple passive circuit. The output power of the power amplifier can be programmed to seven levels. A lock-detect circuit detects when the PLL is in lock. In receive mode, the PLL synthesizer generates the local oscillator (LO) signal. The N, M, and A values that give the LO frequency are stored in the N0, M0, and A0 registers. The receiver is a zero intermediate frequency (IF) type which makes channel filtering possible with low-power, integrated low-pass filters. The receiver consists of a low noise amplifier (LNA) that drives a quadrature mix pair. The mixer outputs feed two identical signal channels in phase quadrature. Each channel includes a pre-amplifier, a third order Sallen-Key RC low-pass filter that protects the following switched-capacitor filter from strong adjacent channel signals, and a limiter. The main channel filter is a switched-capacitor implementation of a six-pole elliptic low pass filter. The cut-off frequency of the Sallen-Key RC filter can be programmed to four different frequencies: 100kHz, 150kHz, 230kHz, and 340kHz. The I and Q channel outputs are demodulated and produce a digital data output. The demodulator detects the relative phase of the I and the Q channel signal. If the I channel signal lags behind the Q channel, the FSK tone frequency is above the LO frequency (data '1'). If the I channel leads the Q channel, the FSK tone is below the LO frequency (data '0'). The output of the receiver is available on the DataIXO pin. A receive signal strength indicator (RSSI) circuit indicates the received signal level. All support documentation can be found on Micrel's web site at www.micrel.com.
RadioWire(R)
Features
* * * * * * * * * True single chip transceiver Digital bit synchronizer Received signal strength indicator (RSSI) RX and TX power management Power down function Reference crystal tuning capabilities Basedband shaping Three-wire programmable serial interface Register read back function
Applications
* * * * * * * Telemetry Remote metering Wireless controller Remote data repeater Remote control systems Wireless modem Wireless security system
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RadioWire(R) RF Transceiver Selection Guide
Device MICRF500 MICRF501 MICRF505 MICRF506 Frequency Range 700MHz - 1.1GHz 300MHz - 440MHz 850MHz - 950MHz 410MHz - 450MHz Maximum Data Rate 128k Baud 128k Baud 200k Baud 200k Baud Receive 12mA 8mA 13mA 12mA Supply Current 2.5 to 3.4V 2.5 to 3.4V 2.0 to 2.5V 2.0 to 2.5V Transmit 50mA 45mA 28mA 21.5mA Modulation Type FSK FSK FSK FSK Package LQFP-44 LQFP-44 MLFTM-32 MLFTM-32
Ordering Information
Part Number MICRF506BML Junction Temp. Range(1) -40 to +85C Package 32-Pin MLFTM
____________________________________________________________________________________________________
Typical Application
2 _ 5 P 2 V 2 _ 5 P 2 V R1 6k2 C3 nc C2 R2 0R 100nF C1 10nF 1 _ 5 P 2 V 5 2D D V G I XTALOUT D XTALIN CS SCLK C9 1.5pF 24 23 22 21 20 19 18 17 Y1 2 2 _ 5 P 2 V
2 _ 5 P 2 V 2 3 C N 1 R3 27k 2 3 4 L1 ANT 50ohm line C6 12nH 15pF 47pF 18pF C5 50ohm line C4 6 7 R4 nc 8 5 RFGND PTATBIAS RFVDD RFGND ANT RFGND GND NC S A I B I C 9 0 0 1 _ 5 P 2 V R5 82k 1 3D D V O C V
0 3D N G O C V
9 2N I R A V
8 2 D N G
7 2T U O _ P C
6 2D N G G I D
4
3
C8 1.5pF CS SCLK IO DATAIXO DATACLK
TSX 10A, 16MHz 1
V2P5_3
MICRF506
MLF32
IO DATAlXO DATACLK
RFVDD
R7 10R
D D V F I 1 1
D N G F I 2 1
T U O H C I 3 1
T U O H C Q 4 1
NC I S S R 5 1
D L 6 1
C N
LD TP1 TP2 RSSI C7 1nF
0 _ 5 P 2 V
1 _ 5 P 2 V C10 1nF
2 _ 5 P 2 V C11 10nF
3 _ 5 P 2 V C12 1nF
C13 1nF
R6 33k
MICRF506 - MLF32
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Pin Configuration
NC VCOVDD VCOGND VARIN GND CPOUT DIGGND DIGVDD
RFGND PTATBIAS RFVDD RFGND ANT RFGND GND NC
1 2 3 4 5 6 7 8
32 3130 29 28 27 26 25 24 23 22 21 20 19 18 17 9 10 11 12 13 14 15 16
CIBIAS IFVDD IFGND ICHOUT QCHOUT RSSI LD NC
XTALOUT XTALIN CS SCLK IO DATAIXO DATACLK NC
32-Pin MLFTM
Pin Description
Pin Number 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 Pin Name RFGND PTATBIAS RFVDD RFGND ANT RFGND RFGND NC CIBIAS IFVDD IFGND ICHOUT QCHOUT RSSI LD NC NC O O O O O I/O O Type Pin Function LNA and PA ground. Connection for bias resistor. LNA and PA power supply. LNA and PA ground. Antenna In/Output. LNA and PA ground. LNA and PA ground. No connect. Connection for bias resistor. IF/mixer power supply. IF/mixer ground. Test pin. Test pin. Received signal strength indicator. PLL lock detect. No connect. No connect 28 29 30 31 32 GND VARIN VCOGND VCOVDD NC I 23 24 25 26 27 XTALIN XTALOUT DIGVDD DIGGND CPOUT O I O 21 22 SCLK CS I/O I Pin Number 18 19 20 Pin Name DATACLK DATAIXO IO Type O I/O I/O Pin Function RX/TX data clock output. RX/TX data input/output. 3-wire interface data in/output. 3-wire interface serial clock. 3-wire interface chip select. Crystal oscillator input. Crystal oscillator output. Digital power supply. Digital ground. PLL charge pump output. Substrate ground. VCO varactor. VCO ground. VCO power supply. No connect.
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Absolute Maximum Ratings(1)
Supply Voltage (VDD)............................................ +3.3V Voltage on any pin (GND = 0V)........ -0.3V to 2.7V Lead Temperature (soldering, 4sec.)................ TBDC Storage Temperature (Ts) ................. -55C to +150C EDS Rating(3)........................................................... 2kV
Operating Ratings(2)
Supply voltage (VIN) .............................. +2.0V to +2.5V RF Frequencies ............................ 410MHz to 450MHz Data Rate (NRZ)......................................... <200kBaud Ambient Temperature (TA) .................. -40C to +85C Package Thermal Resistance MLFTM ( JA) .............................................. 41.7C/W
Electrical Characteristics(4)
fRF = 433MHz. Data-rate = 125kbps, Modulation type = closed-loop VCO modulation, VDD = 2.5V; TA = 25C, bold values indicate -40C< TA < +85C, unless noted.
Symbol Parameter RF Frequency Operating Range Power Supply Power Down Current Standby Current VCO and PLL Section Reference Frequency PLL Lock Time 3kHz bandwidth PLL Lock Time 20kHz bandwidth Switch Time 3kHz loop bandwidth
(5)
Condition
Min 410 2.0
Typ
Max 450 2.5
Units MHz V A A MHz ms ms ms
0.3 280
3 370
4 433.75MHz to 434.25MHz 430MHz to 440MHz 433.75MHz to 434.25MHz Rx - Tx Tx - Rx Standby Rx Standby Tx 0.7 1.3 0.3 1.0 1.0 1.0 1.0 1.0 100 420 125 500
40 1.3 2
1.4 2.5 3
ms ms ms ms ms
Crystal Oscillator Start-Up Time Charge Pump Current
16MHz, 9pF load, 5.6pF loading capacitors VCPOUT = 1.1V, CP_HI = 0 VCPOUT = 1.1V, CP_HI = 1
170 680
A A dBm dBm dB dB mA mA mA
Transmit Section Output Power RLOAD = 500 , Pa2-0-111 RLOAD = 500 , Pa2-0-001 Output Power Tolerance Tx Current Consumption Over temperature range Over power supply range RLOAD = 500 , Pa2-0-111 RLOAD = 500 , Pa2-0-001 RLOAD = 500 , Pa2-0-000 Binary FSK Frequency Separation(5) Data Rate(5) Birate = 200kbps VCO modulation Divider modulation 20 20 11 -7 1 3 21.5 10.5 8.0 500 200 20
kHz kbps kbps
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Symbol
Parameter Occupied bandwidth
(5)
Condition 38.4kbps, 125kbps, 200kbps, = 2, 20dBc = 2, 20dBc = 2, 20dBc
Min
Typ 140 550 800 -16 -8
Max
Units kHz kHz kHz dBm dBm
2 Harmonic 3rd Harmonic Spurious Emission<1GHz(5) Spurious Emission<1GHz Receive Section Rx Current Consumption LNA bypass Switch cap filter bypass with LNA Rx Current Consumption Variation Receiver Sensitivity Over temperature 2.4kbps, 4.8kbps, 19.2kbps, 38.4kbps, 76.8kbps, 125kbps, 200kbps, Receiver Maximum Input Power Receiver Sensitivity Tolerance Receiver Bandwidth Co-Channel Rejection Adjacent Channel Rejection 500kHz spacing 1MHz spacing Blocking 1MHz 2MHz 5MHz 10MHz Noise Figure, Cascade 1dB Compression Input IP3 Input IP2 LO Leakage Spurious Emission Input Impedance(5)
(5) (5)
nd
<-54 <-30 12 9.5 9.5 3 -113 -111 -106 -104 -101 -100 -97 +12 +2 4 1 50 T.B.D. T.B.D. T.B.D. 47 48 39 48 T.B.D. -34 2 tones with 1MHz separation -25 T.B.D. -90 <1GHz >1GHz 50 <-57 <-57 350
dBm dBm mA mA mA mA dBm dBm dBm dBm dBm dBm dBm dBm dBm dB dB kHz dB dB dB dB dB dB dB dB dB dBm dBm dBm dBm dBm
= 16 = 16 =4 =4 =2 =2 =2
125kbps, 125kHz deviation 20kbps, 40kHz deviation Over temperature Over power supply range
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Symbol
Parameter RSSI Dynamic Range RSSI Output Range
Condition Pin = -110dBm Pin = -60dBm
Min
Typ 50 0.9 2
Max
Units dB V V
Digital Inputs/Outputs VIH VIL Logic Input High Logic Input Low Clock/Data Frequency
(5) (5)
0.7VDD 0 45
VDD 0.3VDD 10 55
V V MHz %
Clock/Data Duty Cycle
Notes:
1. Exceeding the absolute maximum rating may damage the device. 2. The device is not guaranteed to function outside its operating rating. 3. Devices are ESD sensitive. Handling precautions recommended. Human body model, 1.5k in series with 100pF. 4. Specification for packaged product only. 5. Guaranteed by design.
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Programming
General The MICRF506 functions are enabled through a number of programming bits. The programming bits are organized as a set of addressable control registers, each register holding 8 bits. There are 23 control registers in total in the MICRF506, and they have addresses ranging from 0 to 22. The user can read all the control registers. The user can write to the first 22 registers (0 to 21); the register 22 is a read-only register. All control registers hold 8 bits and all 8 bits must be written to when accessing a control register, or they will be read. Some of the registers do not utilize all 8 bits. The value of an unused bit is "don't care." The control register with address 0 is referred to as ControlRegister0, the control register with address 1 is ControlRegister1 and so on. A summary of the control registers is given in the table below. In addition to the unused bits (marked with"-") there are a number of fixed bits (marked with "0" or "1"). Always maintain these as shown in the table. The control registers in MICRF506 are accessed through a 3-wire interface; clock, data and chip select. These lines are referred to as SCLK, IO, and CS, respectively. This 3-wire interface is dedicated to control register access and is referred to as the control interface. Received data (via RF) and data to transmit (via RF) are handled by the DataIXO and DatalClk (if enabled) lines; this is referred to as the data interface. The SCLK line is applied externally; access to the control registers are carried out at a rate determined by the user. The MICRF506 will ignore transitions on the SCLK line if the CS line is inactive. The MICRF506 can be put on a bus, sharing clock and data lines with other devices. All control registers should be initiated (written to) following a power-on. During operation, however, writing to one register is sufficient to change the way the transceiver works.
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Adr A6...A0 0000000 0000001 0000010 0000011 0000100 0000101 0000110 0001000 0001001 0001010 0001011 0001100 0001101 0001110 0001111 0010000 0010001 0010010 0010011 0010100 0010101 0010110 D7 LNA_by Modulation1 CP_HI `1' Mod_F2 `1' `0' N0_7 M0_7 N1_7 M1_7 `1' FEE_7 D6 PA2 Modulation2 `0' `1' Mod_F1 Mod_clkS2 ScClk_X2 `1' N0_6 M0_6 N1_6 M1_6 `0' FEE_6 D5 PA1 ol_opamp_en `0' `0' Mod_F0 `0' Mod_clkS1 RefClk_K5 ScClk5 `1' A0_5 N0_5 M0_5 A1_5 N1_5 M1_5 `1' FEE_5 D4 PA0 `0' PA_By VCO_IB2 Mod_I4 `1' RefClk_K4 ScClk4 XCOtune4 A0_4 N0_4 M0_4 A1_4 N1_4 M1_4 `1' FEE_4
Data D3 Sync_en RSSI_en OUTS3 VCO_IB1 Mod_I3 Mod_A3 RefClk_K3 ScClk3 XCOtune3 A0_3 N0_11 N0_3 M0_11 M0_3 A1_3 N1_11 N1_3 M1_11 M1_3 `0' FEEC_3 FEE_3 D2 Mode1 LD_en OUTS2 VCO_IB0 Mod_I2 Mod_A2 RefClk_K2 ScClk2 XCOtune2 A0_2 N0_10 N0_2 M0_10 M0_2 A1_2 N1_10 N1_2 M1_10 M1_2 `1' FEEC_2 FEE_2 D1 Mode0 PF_FC1 OUTS1 VCO_freq1 Mod_I1 Mod_A1 RefClk_K1 ScClk1 XCOtune1 A0_1 N0_9 N0_1 M0_9 M0_1 A1_1 N1_9 N1_1 M1_9 M1_1 `0' FEEC_1 FEE_1 D0 Load_en PF_FC0 OUTS0 VCO_freq0 Mod_I0 Mod_A0 RefClk_K0 ScClk0 XCOtune0 A0_0 N0_8 N0_0 M0_8 M0_0 A1_0 N1_8 N1_0 M1_8 M1_0 `1' FEEC_0 FEE_0
Mod_clkS0 BitSync_clkS2 BitSync_clkS1 BitSync_clkS0 BitRate_clkS2
0000111 BitRate_clkS1 BitRate_clkS0
Table 1. Control Registers in MICRF506
Names of programming bits, unused bits ("-") and fixed bits ("1" or "0") are shown. The control register with address 0 is referred to as ControlRegister0 etc.
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Writing to the control registers in MICRF506 Writing: A number of octets are entered into MICRF506 followed by a load-signal to activate the new setting. Making these events is referred to as a "write sequence." It is possible to update all, 1, or n control registers in a write sequence. The address to write to (or the first address to write to) can be any valid address (0-21). The IO line is always an input to the MICRF506 (output from user) when writing.
What to write: The two different ways to "program the chip" are:
*
Write to a number of control registers (0-22) when the registers have incremental addresses (write to 1, all or n registers) Write to a number of control registers when the registers have non-incremental addresses.
*
Writing to a Single Register Writing to a control register with address "A6. A5, ...A0" is described here. During operation, writing to 1 register is sufficient to change the way the transceiver works. Typical example: Change from receive mode to power-down. What to write:
Field Address: R/W bit: Values: Comments 7 bit = A6, A5, ...A0 (A6 = msb. A0 = lsb) "0" for writing 8 bits = D7, D6, ...D0 (D7 = msb, D0 = lsb) Table 3. "Address" and "R/W bit" together make 1 octet. In addition, 1 octet with programming bits is entered. In total, 2 octets are clocked into the MICRF506. How to write:
*
The address of the control register to write to (or if more than 1 control register should be written to, the address of the 1st control register to write to). A bit to enable reading or writing of the control registers. This bit is called the R/W bit. The values to write into the control register(s).
*
*
What to write:
Field Address: R/W bit: Values: Comments A 7-bit field, ranging from 0 to 21. MSB is written first. A 1-bit field, = "0" for writing A number of octets (1-22 octets). MSB in every octet is written first. The first octet is written to the control register with the specified address (="Address"). The next octet (if there is one) is written to the control register with address = "Address + 1" and so on. Table 2. How to write:
* * *
Bring CS high Use SCLK and IO to clock in the 2 octets Bring CS low
CS
Bring CS active to active to start a write sequence. The active state of the CS line is "high." Use the SCLK/IO serial interface to clock "Address" and "R/W" bit and "Values" into the MICRF506. MICRF506 will sample the IO line at negative edges of SCLK. Make sure to change the state of the IO line before the negative edge. Refer to figures below. Bring CS inactive to make an internal load-signal and complete the write-sequence. Note: there is an exception to this point. If the programming bit called "load_en" (bit0 in ControlRegister0) is "0", then no load pulse is generated. September 2004 9
SCLK IO A6 A5 A0 RW D7 D6 D2 D1 D0
Address of register i
RW
Data to write into register i Internal load pulse made here
Figure 1. In Figure 1, IO is changed at positive edges of SCLK. The MICRF506 samples the IO line at negative edges. The value of the R/W bits is always "0" for writing.
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Writing to All Registers After a power-on, all writable registers should be written. This is described here. Writing to all register can be done at any time. To get the simplest firmware, always write to all registers. The price to pay for the simplicity is increased write-time, which leads to increased time to change the way the MICRF506 works. What to write
Field Address: R/W bit: Values: Comments `000000' (address of the first register to write to, which is 0) "0" for writing 1 Octet: wanted values for ControlRegister0. 2nd Octet: wanted values for ControlRegister1 and so on for all of the octets. So the 22nd octet wants values for ControlRegister21. Refer to the specific sections of this document for actual values. Table 4. "Address" and "R/W bit" together make 1 octet. In addition, 22 octets with programming bits are entered. In total, 23 octets are clocked into the MICRF506. How to write:
st
Writing to n Registers having Incremental Addresses In addition to entering all bytes, it is also possible to enter a set of n bytes, starting from address i = "A6, A5, ... A0". Typical example: Clock in a new set of frequency dividers (i.e. change the RF frequency). "Incremental addresses". Registers to be written are located in i, i+1, i+2. What to write
Field Address: R/W bit: Values: Comments 7 bit = A6, A5, ...A0 (A6 = msb. A0 = lsb) (address of first byte to write to) "0" for writing n* 8 bits = D7, D6, ...D0 (D7 = msb, D0 = lsb) (written to control reg. with address "i") D7, D6, ...D0 (D7 = msb, D0 = lsb) (written to control reg. with address "i+1") D7, D6, ...D0 (D7 = msb, D0 = lsb) (written to control reg. with address "i+n-1") Table 5. "Address" and "R/W bit" together make 1 octet. In addition, n octets with programming bits are entered. Totally, 1 +n octets are clocked into the MICRF506. How to write:
* * *
Bring CS high Use SCLK and IO to clock in the 23 octets Bring CS low
* * *
Bring CS high Use SCLK and IO to clock in the 1 + n octets Bring CS low
Refer to the figure in the next section, "Writing to n registers having incremental addresses".
In Figure 1, IO is changed at positive edges of SCLK. The MICRF506 samples the IO line at negative edges. The value of the R/W bits is always "0" for writing.
CS
SCLK IO A6 A5 A0 RW D7 D6 D2 D1 D0
Address of first register to write to, register i
RW Data to write into register i
Data to write into register i+1
Internal load pulse made here
Figure 2.
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Writing to n Registers having Non-Incremental Addresses Registers with non-incremental addresses can be written to in one write-sequence as well. Example of non-incremental addresses: "0,1,3". However, this requires more overhead, and the user should consider the possibility to make a "continuous" update, for example, by writing to "0,1,2,3" (writing the present value of "2" into "2"). The simplest firmware is achieved by always writing to all registers. Refer to previous sections. This write-sequence is divided into several subparts: * Disable the generation of load-signals by clearing bit "load_en" (bit0 in ControlRegister0) Repeat for each group of register having incremental addresses: o o o o Bring CS active Enter first address for this group, R/W bit and values Bring CS inactive Finally, enable and make a loadsignal by setting "load_en"
Reading n registers from MICRF506
CS
SCLK IO A6 A5 A0 RW D7 D6 D0
Address of register i Simple time
RWData read from reg. i
IO Input IO Output
Figure 3.
In the figure, 1 register is read. The address is A6, A5, ... A0. A6 = msb. The data read out is D7, D6, ...D0. The value of the R/W bit is always "1" for reading. SCLK and IO together form a serial interface. SCLK is applied externally for reading as well as for writing. * * * * * Bring CS active Enter address to read from (or the first address to read from) (7 bits) and The R/W bit = 1 to enable reading Make the IO line an input to the user (set pin in tristate) Read n octets. The first rising edge of SCLK will set the IO as an output from the MICRF506. MICRF will change the IO line at positive edges. The user should read the IO line at the negative edges. Make the IO line an output from the user again.
*
Refer to the previous sections for how to write to 1 or n (with incremental addresses) registers in the MICRF506. Reading from the control registers in MICRF506 The "read-sequence" is: 1. Enter address and R/W bit 2. Change direction of IO line 3. Read out a number of octets and change IO direction back again. It is possible to read all, 1 or n registers. The address to read from (or the first address to read from) can be any valid address (0-22). Reading is not destructive, i.e. values are not changed. The IO line is output from the MICRF506 (input to user) for a part of the read-sequence. Refer to procedure description below. A read-sequence is described for reading n registers, where n is number 1-23.
*
Programming interface timing
Figure 4 and Table 6 shows the timing specification for the 3-wire serial programming interface.
Tcsr
traise tfall
Tper
Thigh Tread Tlow
Twrite
Tscl
SCLK CS
IO
A6
A5
A0
RW
D7
D6
D2
D1
D0
Address Register
Data Register LOAD
Figure 4.
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Values Symbol Tper Thigh Tlow tfall Parameter Min. period of SCLK Min. high time of SCLK Min. low time of SCLK Max. time of falling edge of SCLK Max. time of rising edge of SCLK Max. time of rising edge of CS to falling edge of SCLK Min. delay from rising edge of CS to rising edge of SCLK Min. delay from valid IO to falling edge of SCLK during a write operation Min. delay from rising edge of SCLK to valid IO during a read operation (assuming load capacitance of IO is 25pF) 0 Min. 50 20 20 1 Typ. Max. Units ns ns ns ns
Programming summary * * * * * * * * Use CS, SCLK, and IO to get access to the control registers in MICRF506. SCLK is user-controlled. Write to the MICRF506 at positive edges (MICRF506 reads at negative edges). Read from the MICRF506 at negative edges (MICRF506 writes at positive edges) After power-on: Write to the complete set of control registers. Address field is 7 bits long. Enter msb first. R/W bit is 1 bit long ("1" for read, "0" for write) Address and R/W bit together make 1 octet All control registers are 8 bits long. Enter/read msb in every octet first. Always write 8 bits to/read 8 bits from a control register. This is the case for registers with less than 8 used programming bits as well. Writing: Bring CS high, write address and R/W bit followed by the new values to fill into the addressed control register(s) and bring CS low for loading, i.e. activation of the new control register values ("load_en" = 1). Reading: Bring CS high, write address and R/W bit, set IO as an input, read present contents of the addressed control register(s), bring CS low and set IO an output.
trise Tcsr
1
ns ns
Tcsf
5
ns
* *
Twrite
0
ns
*
75 ns
Tread
*
Table 6. Timing Specification for the 3-wire Programming Interface
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Frequency Synthesizer
A6...A0 0001010 0001011 0001100 0001101 0001110 0001111 0010000 0010001 0010010 0010011 D7 N0_7 M0_7 N1_7 M1_7 D6 N0_6 M0_6 N1_6 M1_6 D5 A0_5 N0_5 M0_5 A1_5 N1_5 M1_5 D4 A0_4 N0_4 M0_4 A1_4 N1_4 M1_4 D3 A0_3 N0_11 N0_3 M0_11 M0_3 A1_3 N1_11 N1_3 M1_11 M1_3 D2 A0_2 N0_10 N0_2 M0_10 M0_2 A1_2 N1_10 N1_2 M1_10 M1_2 D1 A0_1 N0_9 N0_1 M0_9 M0_1 A1_1 N1_9 N1_1 M1_9 M1_1 D0 A0_0 N0_8 N0_0 M0_8 M0_0 A1_0 N1_8 N1_0 M1_8 M1_0
The frequency synthesizer consists of a voltagecontrolled oscillator (VCO), a crystal oscillator, dual modulus prescaler, programmable frequency dividers and a phase-detector. The loop-filter is external for flexibility and can be a simple passive circuit. The lengths of the N, M, and A registers are12, 12 and 6 respectively. The M, N, and A values can be calculated from the formula:
fXCO fVCO f 4 = = RF M 31 N + A 31 N + A
required. The schematic of the crystal oscillator's external components for 16MHz are shown in Figure 5.
Pin 24 XTALOUT Y1 TSX-10A Pin 23 XTALIN
C10 5.6pF
C11 5.6pF
fPDH =
Figure 5. Crystal Oscillator Circuit
where fPhD is the phase detector comparison frequency. PhD: Phase detector comparison frequency fxco: Crystal oscillator frequency fvco: Voltage controlled oscillator frequency There are two sets of each of the divide factors (i.e. A0 and A1). If modulation by using the dividers is selected (that is Modulation1=1, Modulation0=0), the two sets should be programmed to give two RF frequencies, separated by two times the specified frequency deviation. For all other modulation methods, and also in receive mode, the 0-set will be used.
The crystal should be connected between pins XosIn and XoscOut (pin 23 and 23). In addition, loading capacitors for the crystal are required. The loading capacitor values depend on the total load capacitance, CL, specified for the crystal. The load capacitance seen between the crystal terminals should be equal to CL for the crystal to oscillate at the specified frequency.
CL = 1 + Cparasitic 1 1 + C10 C11
The parasitic capacitance is the pin input capacitance and PCB stray capacitance. Typically, the total parasitic capacitance is around 6pF. For instance, for a 9pF load crystal the recommended values of the external load capacitors are 5.6pF. It is also possible to tune the crystal oscillator internally by switching in internal capacitance using 5 tune bits XCOtune4 - XCOtun0. When XCOtune4 - XCOtune0 = 0 no internal capacitors are connected to the crystal pins. When XCOtune4 - XCOtune0 = 1 all of the internal capacitors are connected to the crystal pins. Figure 3 shows the tuning range for two different capacitor values, there are 1.5pF and no capacitors. Specification: Package TSX-10A, Nominal frequency 13
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Crystal Oscillator (XCO)
Adr 0001001 D7 `0' D6 `1' D5 `1' D4 D3 D2 D1 XCOtune1 D0 XCOtune0 XCOtune4 XCOtune3 XCOtune2
The crystal oscillator is a very critical block. As the crystal oscillator is a reference for the RF output frequency and also for the LO frequency in the receiver, very good phase and frequency stability is The crystal used is a TN4-26011 from Toyocom. September 2004
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16.000000 MHz, frequency tolerance 10ppm, frequency stability 9ppm, load capacitance 9pF, pulling sensitivity 15ppm/pF.
100,0 80,0 60,0 40,0
VCO
A6..A0 0000011 D7 `1' D6 `1' D5 `0' D4 VCO_IB2 D3 VCO_IB1 D2 VCO_IB0 D1 VCO_freq1 D0 VCO_freq0
The VCO has no external components. If has three bit to set the bias current and two bit to set the VCO frequency. These five bit are set by the RF frequency, as follows:
2x1.5pF 2x0pF
[ppm]
20,0 0,0 -20,0 -40,0 -60,0 0 8 16 XCO bitvalue 24 32
RF freq. 410MHz 410-423MHz 423-436MHz 436-450MHz
VCO_IB2 1 0 0 0
VCO_IB1 1 1 0 0
VCO_IB0 1 1 1 0
VCO_freq1 VCO_freq0 0 0 1 1 0 1 0 1
Table 8. VCO Bit Setting
Figure 6. XCO Tuning
The start up time is given in Table 7. As can be seen, more capacitance will slow down the start up time. The start-up time of a crystal oscillator is typically around a millisecond. Therefore, to save current consumption, the XCO is turned on before any other circuit block. During start-up the XCO amplitude will eventually reach a sufficient level to trigger the Mcounter. After counting 2 M-counter output pulses the rest of the circuit will be turned on. The current consumption during the prestart period is approximately 280A.
XCO Bitvalue 0 1 2 4 8 16 31 Start-up Time (ms) 590 590 700 700
The bias bit will optimize the phase noise, and the frequency bit will control a capacitor bank in the VCO. The tuning range, the RF frequency versus varactor voltage, is dependent on the VCO frequency setting, and can be shown in Figure 7. When the tuning voltage is in the range from 0.9V to 1.4V, the VCO gain is at its maximum, approximately 32 to 35MHz/V. It is recommended that the varactor voltage stays in this range. The input capacitance at the varactor pin must be taken into consideration when designing the PLL loop filter. This is most critical when designing a loop filter with high bandwidth, which gives relatively small component values. The input capacitance is approximately 6pF.
VCO frequency gain, Vdd=2.5V
480 470 460 450
Freq [MHz]
810 1140 2050
440 430 420 410 400 390 380 0 0.4 0.8 1.2 V_varactor [V] 1.6 2 2.4
11 10 01 00
Table 7. Typical values with CEXT = 1.5pF
If an external reference is used instead of a crystal, the signal shall be applied to pin 24, XtalOut. Due to internal DC setting in the XCO, an AC coupling is recommended to be used between the external reference and the XtalOut-pin.
Figure 7. RF Frequency vs. Varactor Voltage and VCO Frequency bit (VDD = 2.25V)
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Charge Pump
A6..A0 0000011 D7 CP_HI D6 `0' D5 `0' D4 `0' D3 OUTS3 D2 OUTS2 D1 OUTS1 D0 OUTS1
The charge pump current can be set to either 125A or 500A by CP_HI (`1' D 500A). This will affect the loop filter component values, see "PLL Filter" section. In most cases, the lowest current is best suited. For applications using phase detector frequency and high PLL bandwidth, the 500A can be a better choice.
PLL Filter
The design of the PLL filter will strongly affect the performance of the frequency synthesizer. The PLL filter is kept externally for flexibility. Input parameters when designing the loop filter for the MICRF506 are mainly the modulation method and the bit rate. These choices will also affect the switching time and phase noise. The frequency modulation can be done in two different ways with the MICRF506, either by VCO modulation or by modulation with the internal dividers (see chapter Frequency modulation for further details). In the first case, the PLL needs to lock on a new carrier frequency for every new data bit. Now the PLL bandwidth needs to be adequately high. It may be necessary to use a third order filter to suppress the phase detector frequency, as this is not suppressed as much as when doing modulation on the VCO. A schematic for a second and third order loop filter is shown in Figure 8. Schematic for open loop modulation is shown in Figure 9.
Pin 27 CP_OUT Pin 29 VARIN
Table 9 shows three different loop filters, the two first for VCO modulation and the last one for modulation using the internal dividers. The component values are calculated with RF frequency = 434MHz, VCO gain = 32MHz/V and charge pump current = 125A. Other settings are shown in the table. The varactor pin capacitance (pin 29) of 6pF does not influence on the component values for the two filters with lowest bandwidth. For the 12kHz bandwidth filter, a third order loop filter is calculated. The third pole is set by R2xC3. Here C3 is chosen to be 6pF, the same as the varactor input pin capacitance (pin 29). C3 can therefore be skipped.
Phase PLL Phase Detector BW Margin() Freq. (kHz) (kHz) 0.6 3 5 10 56 56 70 56 100 100 500 100
Baud Rate (kbaud/sec) VCO VCO Divider Open-loop >38.4 >125 <20 <200
C1
C2
R1
R2
C3
10nF 680pF 150pF 150pF
100nF 6.8nF 10nF 1.5nF
6.2k_ 22k_ 18k_ 36k_
0 0 82k_ NC
NC NC 4.7pF 100nF
Table 9. Loop Filter Components Values
Lock Detect
A6..A0 0000001 D7 Modulation1 D6 Modulation0 D5 `0' D4 `0' D3 RSSI_en D2 LD_en D1 PF_FC1 D0 PF_FC0
A lock detector can be enabled by setting LD_en = 1. When pin LD is high, it indicates that the PLL is in lock.
Modes of Operation
A6..A0 0000000 D7 LNA_by D6 PA2 D5 PA1 D4 PA0 D3 Sync_en D2 Mode1 D1 Mode0 D0 Load_en
Mode1 0 0 1 1
Mode0 0 1 0 1
State Power down Standby Receive Transmit
Comments Keeps register configuration Only crystal oscillator running Full receive Full transmit ex PA state
R2
C1
C2 R1
C3
Figure 8. Second and Third Order Loop Filter
PIN 27, CP_OUT C1 C2 R1 C3
PIN 29, VAR_IN
Figure 9. Loop filter for open loop modulation
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Transceiver Sync/Non-Synchronous Mode
A6..A0 0000000 0000110 0000111 D7 LNA_by BitRate_clkS1 D6 PA2 Mod_clkS2 BitRate_clkS0 D5 PA1 Mod_clkS1 RefClk_K5 D4 PA0 Mod_clkS0 RefClk_K4 D3 Sync_en BitSync_clkS2 RefClk_K3 D2 Mode1 BitSync_clkS1 RefClk_K2 D1 Mode0 BitSync_clkS0 RefClk_K1 D0 Load_en BitRate_clkS2 RefClk_K0
Sync_en 0 0 1 1
State Rx: Bit synchronization off Tx: DataClk pin off Rx: Bit synchronization on Tx: DataClk pin on
Comments Transparent reception of data Transparent transmission of data Bit-clock is generated by transceiver Bit-clock is generated by transceiver
When Sync_en = 1, it will enable the bit synchronizer in receive mode. The bit synchronizer clock needs to be programmed, see chapter Bit synchronizer. The synchronized clock will be set out on pit DataClk. In transmit mode, when Sync_en = 1, the clock signal on pin DataClk is a programmed bit rate clock. Now the transceiver controls the actual data rate. The data to be transmitted will be sampled on rising edge of DataClk. The micro controller can therefore use the negative edge to change the data to be transmitted. The clock used for this purpose, BitRate-clock, is programmed in the same way as the modulator clock and the bit synchronizer clock:
fBITRATE_CLK = fXCO Refclk_K 2 (7-BITRATE_clkS )
MICRF506 is defined as "Master" and provides a data clock that allows users to utilize low cost micro controller reference frequency. The data interface is defined in such a way that all user actions should take place on falling edge and is illustrated Figure 9 and 10. The two figures illustrate the relationship between DATACLK and DATAIXO in receive mode and transmit mode. MICRF506 will present data on rising edge and the "USER" sample data on falling edge in receive mode.
DATAIXO
DATACLK
where: fBITRATE_CLK: The clock frequency used to control the bit rate, should be equal to the bit rate (bit rate of 20 kbit/sec requires a clock requency of 20kHz) fxco: Crystal oscillator frequency Refclk_K: 6 bit divider, values between 1 and 63 BitRate_clkS: Bit rate setting, values between 0 and 6 Data Interface The MICRF506 interface can be divided in to two separate interfaces, a "programming interface" and a "Data interface". The "programming interface" has a three wire serial programmable interface and is described in chapter Programming. The "data interface" can be programmed to sync/non-synchronous mode. In synchronous mode the September 2004 16
Figure 10. Data interface in Receive Mode
The User presents data on falling edge and MICRF506 samples on rising edge in transmit mode.
DATAIXO
DATACLK
Figure 11. Data interface in Transmit Mode
When entering transmit mode it is important to keep DATAIXO in tri-state from the time Tx-mode is entered until user starts sending data. The data is provided directly to the modulation circuit and violation of this may/will cause abnormal behavior. Depending upon the chosen FSK modulation, some sort of encoding might be needed. The different modulation types and encoding is described in chapter Frequency modulation.
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Receiver The receiver is a zero intermediate frequency (IF) type in order to make channel filtering possible with low-power integrated low-pass filters. The receiver consists of a low noise amplifier (LNA) that drives a quadrature mixer pair. The mixer outputs feed two identical signal channels in phase quadrature. Each channel include a pre-amplifier, a third order SallenKey RC lowpass filter from strong adjacent channel signals and finally a limiter. The main channel filter is a switched-capacitor implementation of a six-pole elliptic lowpass filte. The elliptic filter minimizes the total capacitance required for a given selectivity and dynamic range. The cut-off frequency of the SallenKey RC filter can be programmed to four different frequencies: 100kHz, 150kHz, 230kHz and 340kHz. The demodulator demodulates the I and Q channel outputs and produces a digital data output. If detects the relative phase of the I and Q channel signal. If the I channel signal lags the Q channel, the FSK tone frequency lies above the LO frequency (data `1'). If the I channel leads the Q channel, the FSK tone lies below the LO frequency (data `0'). The output of the receiver is available on the DataIXO pin. A RSSI circuit (receive signal strength indicator) indicates the received signal level.
Figure 12. LNA Input Impedance
Sallen-Key Filters
A6..A0 0000001 D7 Modulation1 D6 Modulation0 D5 `0' D4 `0' D3 RSSI_en D2 LD_en D1 PF_FC1 D0 PF_FC0
Front End
A6..A0 0000000 D7 LNA_by D6 PA2 D5 PA1 D4 PA0 D3 Sync_en D2 Mode1 D1 Mode0 D0 Load_en
A low noise amplifier in RF receivers is used to boost the incoming signal prior to the frequency conversion process. This is important in order to prevent mixer noise from dominating the overall front-end noise performance. The LNA is a twostage amplifier and has a nominal gain of approximately 23dB at 434MHz. The front end has a gain of about 35dB to 38dB. The gain varies by 11.5dB over a 2.0V to 2.5V variation in power supply. The LNA can be bypassed by setting bit LNA_by to `1'. This can be useful for very strong input signal levels. The front-end gain with the LNA bypassed is about 12dB. The mixers have a going of about 10dB at 434MHz. The differential outputs of the mixers can be made available at pins IchOut and QchOut. The output impedance of each mixer is about 8k_. The input impedance is close to 50_ as shown in Figure 12, giving an input reflection of about -20dB. The receiver does not require any matching network.
Each channel includes a pre-amplifier and a prefilter, which is a three-pole Sallen-Key lowpass filter. It protects the following switched-capacitor filter from strong adjacent channel signals, and it also works as an anti-aliasing filter. The preamplifier has a gain of 22.23dB. The maximum output voltage swing is about 1.4Vpp for a 2.25V power supply. In addition, the IF amplifier also performs offset cancellation. Gain varies by less than 0.5dB over a 2.0 - 2.5V variation in power supply. The third order Sallen-Key lowpass filter is programmable to four different cutoff frequencies according to the table below:
PF_FC1 0 0 1 1 PF_FC0 0 1 0 1 Cut-off Freq. (kHz) 100 150 230 340
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Switched Capacitor Filter
A6..A0 0001000 D7 `1' D6 ScClk_X2 D5 ScClk5 D4 ScClk4 D3 ScClk3 D2 ScClk2 D1 ScClk1 D0 ScClk0
where fBW: Needed receiver bandwidth, fcut above should not be smaller than fBW (Hz) foffset: Total frequency offset between receiver and transmitter (Hz) fDEV: Single-sided frequency deviation, see chapter Modulator on how to calculate (Hz) Baudrate: The baud rate given is bit/sec
The main channel filter is a switched-capacitor implementation of a six-pole elliptic low pass filter. The elliptic filter minimized the total capacitance required for a given selectivity and dynamic range. The cut-off frequency of the switched-capacitor filter is adjustable by changing the clock frequency. The clock frequency is designed to be 20 times the cut-off frequency. The clock frequency is derived from the reference crystal oscillator. A programmable 6-bit divider divides the frequency of the crystal oscillator. To generate the correct nonoverlapping clock-phases needed by the filter this frequency is then divided by 4. The cut-off frequency of the filter is given by:
fXCO 80 ScClk
RSSI
A6..A0 0000001 D7 Modulation1 D6 Modulation0 D5 `0' D4 `0' D3 RSSI_en D2 LD_en D1 PF_FC1 D0 PF_FC0
RSSI
33kohm, 1nF, 125kbps, BW=200kHz, Vdd=2.5V
2.2 2 1.8
RSSI [V]
1.6 1.4 1.2 1 0.8 0.6 -125 -115 -105 -95 -85 -75 Pin [dBm] -65 -55 -45 -35 -25
fCUT =
when ScClk_X2=0 and
fXCO ScClk
fCUT =
40
Figure 13. RSSI Voltage
when SCClk_X2=1 where: fCUT: Filter cutoff frequency fXCO: Crystal oscillator frequency ScCLK: Switched capacitor filter clock, bits ScClk5-0 For instance, for a crystal frequency of 32MHz and if the 6 bit divider divides the input frequency by 5 the cut-off frequency of the SC filter is 32MHz/(80 x 5) = 80MHz. 1st order RC lowpass filters are connected to the output of the SC filter-to-filter the clock frequency. The lowest cutoff frequency in the pre- and the main channel filter must be set so that the received signal is passed with no attenuation, which is frequency deviation plus modulation. If there are any frequency offset between the transmitter and the receiver, this must also be taken into consideration. A formula for the receiver bandwidth can be summarized as follows:
fBW = + fOFFSET + fDEV + Baudrate / 2
Pin 14 RSSI
RSSI
R2 33k
C10 1nF
Figure 14. RSSI Network
A Typical plot of the RSSI voltage as function of input power is shown in Figure 13. The RSSI has a dynamic range of about 50dB from about -110dBm to -60dBm input power. The RSSI can be used as a signal presence indicator. When a RF signal is received, the RSSI output increases. This could be used to wake up circuitry that is normally in a sleep mode configuration to conserve battery life. Another application for which the RSSI could be used is to determine if transmit power can be reduced in a system. If the RSSI detects a strong signal, if could tell the transmitter to reduce the transmit power to reduce current consumption. 18
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FEE
A6..A0 0010101 0010110 D7 FEE_7 D6 FEE_6 D5 FEE_5 D4 FEE_4 D3 FEEC_3 FEE_3 D2 FEEC_2 FEE_2 D1 FEEC_1 FEE_1 D0 FEEC_0 FEE_0
Mode UP+DN: Foffset = R/(4P)x(FEE)
The Frequency Error Estimator (FEE) uses information from the demodulator to calculate the frequency offset between it's receive frequency and the transmitter frequency. The output of the FEE can be used to tune the XCO frequency, both for production calibration and for compensation for crystal temperature drift and aging. The inputs to the FEE circuit are the up and down pulses from the demodulator. Every time a `1' is updated, an UP-pulse is coming out of the demodulator, and the same with the DN-pulse every time the `0' is updated. The expected number of pulses for every received symbol is 2 times the modulation index (_). The FEE can operate in three different modes; counting only UP-pulses, only DN-pulses or counting UP+DN pulses. The number of received symbols to be counted is either 8, 16, 32 or 64. This is set by the FEEC_0...FEEC_3 control bit, as follows:
FEEC_1 0 0 1 1 FEEC_3 0 0 1 1 FEEC_0 0 1 0 1 FEEC_2 0 1 0 1 FEE Mode Off Counting UP pulses Counting DN pulses Counting UP and DN pulses. UP increments the counter, DN decrements it. No. of symbols used for the measurement 8 16 32 65
where FEE is the value stored in the FEE register, (Fp is the single sided frequency deviation, P is the number of symbols/data bit counted and R is the symbol/data rate. A positive Foffset means that the received signal has a higher frequency than the receiver frequency. To compensate for this, the receivers XCO frequency should be increased (see ANNEX A) on how to tune the XCO frequency based on the FEE value). It is recommended to use Mode UP+DN for two reasons, you do not need to know the actual frequency deviation and this mode gives the best accuracy.
Table 10. FEEC Control Bit
The result of the measurement is the FEE value, this can be read from register with address 0010110b. Negative values are stored as a binary no between 0000000 and 1111111. To calculate the negative value, a two's complement of this value must be performed. Only FEE modes where DN-pulses are counted (10 and 11) will give a negative value. When the FEE value has been read, the frequency offset can be calculated as follows: Mode UP: Mode DN: September 2004 Foffset = R/(2P)x(FEE-_Fp) Foffset = R/(2P)x(FEE+_Fp) 19
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Bit Synchronizer
A6..A0 0000110 0000111 D7 BitRate_clkS1 D6 ModclkS2 BitRate_clkS0 D5 ModclkS1 RefClk_K5 D4 ModclkS0 RefClk_K4 D3 BitSync_clkS2 RefClk_K3 D2 BitSync_clkS1 RefClk_K2 D1 BitSync_clkS0 RefClk_K1 D0 BitRate_clkS2 RefClk_K0
A bit synchronizer can be enabled in receive mode by selecting the synchronous mode (Sync_en=1). The DataClk pin will output a clock with twice the frequency of the bit rate (a bit rate of 20 kbit/sec gives a DataClk of 20 kHz). A received symbol/bit on DataIXO will be output on rising edge of DataClk. The micro controller should therefore sample the symbol/bit on falling edge of DataClk. The bit synchronizer uses a clock which needs to be programmed according to the bit rate. The clock frequency should be 16 times the actual bit rate (a bit rate of 20 kbit/sec needs a bit synchronizer clock with frequency of 320 kHz). The clock frequency is set by the following formula:
fXCO 2 (7-BITSYNC_clkS )
where fBITSYNC_CLK: The bit synchronizer clock frequency (16 times higher than the bit rate) fXCO: Crystal oscillator frequency bit divider, values Refclk_K: 6 between 1 and 63
BitSync_clkS: Bit synchronizer setting, values between 0 and 7 Refclk_K is also used to derive the modulator clock and the bit rate clock. At the beginning of a received data package, the bit synchronizer clock frequency is not synchronized to the bit rate. When these two are maximum offset to each other, it takes 22 bit/symbols before synchronization is achieved.
fBITSYNC_CLK =
Refclk_K
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Transmitter
Power Amplifier
A6..A0 0000000 0000001 D7 LNA_by Modulation1 D6 PA2 Modulation0 D5 PA1 `0' D4 PA0 `0' D3 Sync_en RSSI_en D2 Mode1 LD_en D1 Mode0 PF_FC1 D0 Load_en PF_FC0
The maximum output power is approximately 10dBm for a 50_ load. For maximum output power the load seen by the PA must be resistive. Higher output power can be obtained by decreasing the load impedance. However, this will be in conflict with obtaining impedance match in the LNA. The output power is programmable in seven steps, with approximately 3dB between each step. This is controlled by bits PA2 - PA0. PA2 - PA0 = 1 give the maximum output power. The power amplifier can be turned off by setting PA2 - PA0 = 0. For all other combinations the PA is on and has maximum power when PA2 - PA0 = 1. The output power varies about 3dB over power supply 2.0V to 2.5V and about 2dB over temperature -40C to +85C. The 2nd and 3rd harmonic of the PA are as follows: 2nd harmonic: 3 harmonic:
rd
Modulation1 0 0 1 1
Modulation0 0 1 0 1
Modulation Type Closed loop modulation using modulator Not in use FSK applied using two sets of dividers Not in use
Table 11. Modulation Bit Setting
<-16dBm <-8dBm
To reduce the emission of harmonics, an LC filter can be added between the ANT pin and the antenna as shown in Figure 15.
When Modulation1 and Modulation0 is 00, the modulator needs to be programmed properly, see "Modulator" section. The modulation signal will now be applied directly on the phase locked VCO. It is therefore important that the PLL bandwidth is not too high, as this will remove the modulation. See "PLL Filter" section on how to calculate the PLL components. When using the modulator the modulation signal is applied to the VCO and therefore some sort of encoding is needed. The level of encoding is determined by the PLL loop filter bandwidth and data rate. Two of the most common encoding techniques are Manchester encoding and 3B4B. Other encoding schemes may also be used. Manchester encoding is when one bit is encoded in to a two-bit word and is shown in Table 10. When using Manchester encoding the maximum overhead is 100%. When selecting PLL loop filter it is important to note that the min baud rate is equal to:
fbaud_min = baud /s 4
C5 ANT 47pF C4 18pF
L1 12nH 15pF C6
Figure 15. LC Filter
This filter is designed for the 434MHz band with 50Ohm terminations. The component values may have to be tuned to compensate for the layout parasitics. This filter may also increase the receiver selectivity. Frequency Modulation
A6..A0 0000001 D7 Modulation1 D6 Modulation0 D5 `0' D4 `0' D3 RSSI_en D2 LD_en D1 PF_FC1 D0 PF_FC0
fbaud_min: The minimum frequency of the baud rate (Hz) baud/s: Elements per second (encoded data)
Data "0" "1" Word "10" "01"
Table 12. Manchester Encoding
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Another much more efficient encoding type is 3B4B where three data bits are encoded into a four-bit word. The reason for encoding is to minimize the dc component in the modulated data. To have minimum dc component each four bit word should include two elements of "1" and two elements of "0". Following this guidance only 6 out of 8 word complies and two encoded words needs special precaution. Whenever 000 and 111 data appear, the user must set/clear a flag that indicate if last encoded word was "Word A" and select the respective encoded word shown in Table 11.
Data 000 001 010 011 100 101 110 111 Word A 1011 1100 0011 1010 0101 1001 Word B 0100
The modulation is applied using the modulator described in chapter Modulator, but since the loop is open during modulation any kind of encoding is allowed (NRZ, Manchester, 3B4B etc). It is important to notice that after end of transmission the DataIxO should be in last valid logic state before the PA stage is turned off. This is to avoid spurious emission. When using open-loop modulation a deviation offset is present and has to be included in the total deviation calculation. Figure 18 illustrate the relationship between the frequency offset and deviation. The drift of the carrier over temperature is measured as shown in Figure 17. The loop bandwidth is around 10kHz and the capacitor on the VarIn pin is 68nF X5R.
Drift of carrrier in openloop modulation (Hz/ms) Vdd=2.5V
18 16 14
Frequency (Hz)
0110 1101 Table 13. 3B4B Encoding 0010
12 10 8 6 4 2 0 -40 -20 0 20 40 60 80 100 Temperature (deg C)
Data bits 000 000 000 000 000 111 111 010 110 000
Encoded words 1011 0100 1011 0100 1011 1101 0010 0011 0110 1011
Comments A Flag indicates if "Word A" has been used A Flag indicates if "Word A" has been used
20
Figure 17. Open loop leakage
Deviation
Table 14. Example of 3B4B encoding
0 0 100 200 300 400 500 600 700 800 900
When modulation is selected (Mode1,Mode0=01), the output of the charge pump will be tristated if DataIXO is either high or low. If DataIXO is tristated, the PLL is active. When the PLL is opened the varactor voltage will decrease with time due to leakage and external capacitor is connected to pin VarIn to minimize it as shown in Figure 16.
PIN 27, CP_OUT C1 C2 R1 C3 PIN 29, VAR_IN
-20
Offset [kHz]
-40
-60
-80
-100
-120 Peak-to-peak deviation [kHz] MOD_A=0 MOD_A=1 MOD_A=2
Figure 18. Open loop, frequency offset
Figure 16.
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When Modulation1 Modulation0 is 10, two sets of divider values need to be programmed. The formula for calculating the M, N and A values is given in chapter Frequency synthesizer. The divider values stored in the M0-, N0-, and A0- registers will be used when transmitting a `0' and the M1-, N1-, and A1registers will be used to transmit a `1'. The difference between the two carrier frequencies corresponds to the double sided frequency modulation. Opposite from the modulation with the modulator, the PLL shall now lock on a new frequency for every change in the transmitted data. The PLL bandwidth therefore needs to be relatively high, higher bit rate requires a higher PLL bandwidth and vice versa. The data to be transmitted shall be applied to pin DataIXO (see chapter Transceiver sync-/non-synchronous mode
on how to use the pin DataClk). The DataIXO pin is set as input in transmit mode and output in receive mode. When set as input, a weak voltage divider will set the level to Vdd/2, when it is not pulled up or down by the controller. When using the modulator, it is important that the DataIXO is kept tristated until the transmission shall begin (when PLL is in lock and the PA is turned on). When Data IXO is tristated, the PLL will lock on the LO frequency (used in receive mode). When DataIXO is set either high or low, the RF frequency will be shifted up or down, centered around the LO-frequency. This is only important when using the modulator, for the other modulation method, if DataIXO is tristated, the M0-, N0- and A0-registers will be used.
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Modulator
A6..A0 0000100 0000101 0000110 0000111 D7 Mod_F2 BitRate_clkS1 D6 Mod_F1 Mod_clkS2 BitRate_clkS0 D5 Mod_F0 `0' Mod_clkS1 RefClk_K5 D4 Mod_I4 `1' Mod_clkS0 RefClk_K4 D3 Mod_I3 Mod_A3 BitSync_clkS2 RefClk_K3 D2 Mod_I2 Mod_A2 BitSync_clkS1 RefClk_K2 D1 Mod_I1 Mod_A1 BitSync_clkS0 RefClk_K1 D0 Mod_I0 Mod_A0 BitRate_clkS2 RefClk_K0
The modulator will create a waveform with programmable amplitude and frequency. This waveform is fed into a modulation varactor in the VCO, which will create the desired frequency modulation. The frequency spectrum can be narrowed by increasing the rise-and fall times of the waveform. The modulator waveform is created by charging and discharging a capacitor. A modulator clock controls the timing, as shown in Figure19. For every rise-and fall edge, 4 clock periods are being used. The charging current during these 4 clock periods are not equal, this is to reduce the high frequency components in the waveform, which in turn will narrow the frequency spectrum. The frequency deviation can be set in three different ways, as will be explained below. A formula for setting the desired deviation is given at the end of this chapter.
Modulator Clock Modulator Waveform
Mod_clka Mod_clkb
Mod_clkb > Mod_clka
Figure 20. Two Different Modulator Clock Setting
A fMOD_CLK of 8 times the bit rate (as in Figure 20) corresponds to a signal filtered in a gaussian filter with a Bandwidth (Period-product (BT)) of 1. When BT is increased, the waveform will be less filtered. Minimum BT is 1 (Mod_clk is 8 times the bitrate). Figure 20 shows two waveforms with BT=1 and BT=2, i.e. the Mod_clk is 8 and 16 times higher than the bit rate. When changing the BT factor, the charge-and discharge times will also be changed, and therefore the frequency deviation, as shown in Figure 19. Modulator Current The current used during the rise- and fall times can be programmed with the Mod_I4..Mod_I0 bit, the last one being LSB. Figure 21 shows two waveforms generated with two different currents, where Mod _ Ia > Mod _ Ib . Higher current will give a higher frequency deviation and vice versa. The effect of modulator clock and MOD_1 is illustrated by:
MOD_1 fMOD_CLK
Figure 19. Modulator Waveform and Clock
Modulator Clock The modulator clock frequency is set by:
fXCO Refclk_K 2 (7
fMod_clk =
fDEVIATION
Mod_clkS )
where fMOD_CLK is the modulator clock shown in Figure 19, fXCO is the crystal oscillator frequency Refclk_K is a 6 bit number and Mod_clkS is a 3 bit number. Mod_clkS can be set to a value between 0 and 7. The modulator clock frequency should be set according to the bit rate and shaping. September 2004 24
To avoid saturation in the modulator it is important not to exceed maximum Mod_I. Maximum Mod_I for a given fMOD_clk is given by:
MOD_IMAX = INT(fMOD_CLK 28 10 6 ) - 1
M9999-092904 (408) 955-1690
Micrel
MICRF506
where INT() returns the integer part of the argument.
Mod_filter on Mod_filter off
Mod_la Mod_lb
Mod_la > Mod_lb
Figure 23. Modulator Waveform with and without Filtering
Figure 21. Two Different Modulator Current Settings
Modulator Attenuator A third way to set the deviation is by programming the modulator attenuator, Mod_A2..Mod_A0, the last being LSB. The purpose of the attenuator is to allow small deviations when the bit rate is small and/or the BT is small (these settings will give a relatively slow modulator clock, and therefore long rise- and fall times, which in turn results in large frequency deviations). In addition, the attenuator will improve the resolution in the modulator.
Mod_Aa Mod_Ab
Mod_F=0 disables the modulator filter and Mod_F=7 gives most filtering. Figure 22 shows a waveform with and without the filter. Calculation of the Frequency Deviation The parameters influencing the frequency deviation can be summarized in the following equations:
fMOD_CLK = fXCO Refclk_K 2 (7
1 1+ Mod_A
Mod_clkS )
fDEV =
Mod_I fMOD_CLK
(C1 + C 2
fRF )
Where: fDEV: Single sided frequency deviation [Hz] Crystal oscillator frequency [Hz] Center frequency [Hz] 6 bit divider, values between 1 and 63 Modulator clock setting, values between 0 and 7 Modulator clock frequency, derived from the crystal frequency, Refclk_K and Mod_clkS Modulator current setting, values between 0 and 31 Modulator attenuator setting, values between 0 and 15 -2.17_1010 82
Mod_Ab > Mod_Ab
fXCO: fRF:
Figure 22. Two Different Modulator Attenuator Settings
Refclk_K: Mod_clkS: fMOD_CLK:
The effect of the attenuator is given by:
1 1+ Mod_A
fDEVIATION
Mod_I: - Figure 22 shows two waveforms with different M < attenuator setting: od_A a M od_A b . If mod_A is increased, the frequency deviation is lowered and vice versa. Modulator Filter To reduce the high-frequency components in the generated waveform, a filter with programmable cutoff frequency can be enabled. This is done using Mod_F2..Mod_F0, the least one being LSB. The Mod_F should be set according to the formula: September 2004 25 Mod_A: C1: C2:
M9999-092904 (408) 955-1690
Micrel
100,0 80,0 60,0 40,0
MICRF506
The modulator filter will not influence on the frequency deviation as long as the programmed cutoff frequency is above the actual bit rate. The frequency deviation must be programmed so that the modulation index (2 x single sided frequency deviation/Baudrate [bps]) always is greater than or equal to 2 including the total frequency offset between the receiver and the transmitter:
fDEV = Baudrate + fOFFSET
[ppm]
20,0 0,0 -20,0 -40,0 -60,0 0 8 16 XCO bitvalue 24 32
2x1.5pF 2x0pF
The calculated fDEV should be used to calculate the needed receiver bandwidth, see chapter Switched capacitor filter.
Figure 25. XCO Tuning
Using the XCO-tune Bits The RF chip has a built-in mechanism for tuning the frequency of the crystal oscillator and is often used in combination with the Frequency Error Estimator (FEE). The XCO tuning is designed to eliminate or reduce initial frequency tolerance of the crystal and/or the frequency stability over temperature.
A procedure for using the XCOtuning feature in combination with the FEE is given below. The MICRF506 measures the frequency offset between the demodulated signal and the Lo and tune the XCO so the Lo frequency is equal to received carrier frequency. A procedure like this can be called during production (storing the calibrated XCO_tune value), at regular intervals or implemented in the communication protocol when the frequency has changed. The FEE can count "UP"-pulses and/or "DOWN"pulses (pulses out of the demodulator when a logic "1" or logic "0", resp.., is received). The FEE can count pulses for n bits, where n = 8, 16, 32 or 64. Example: In FEE, count up+down pulses, counting 8 bits: A perfect case ==> FEE = 0 If FEE > 0: LO is too low, increase LO by decreasing XCO_tune value v.v. for FEE < 0 FEE field holds a number in the range -128, ... , 127. However, it keeps counting above/below the range, which is: If FEE = -128 and still counting dwn-pulses: 1) =>-129 = +127 2) 126 3) 125 ...
Pin 24 XT ALOUT C10 1.5pF Y1 TSX -10A C11 1.5pF
Pin 23 XT ALIN
Figure 24. Crystal oscillator's external components
If the value in XCO_tune is increased (adding capacitance), the frequency will decrease. The XCO uses two external capacitors. The value of these will strongly affect the tuning range. With a 16.0 MHz crystal (TN4-26011 from Toyocom), and external capacitor values of 1.5 pF, the tuning range will be (almost) equally divided between Oincrease frequencyO and Odecrease frequencyO. That is, XCO_tune values greater than approx 16 will decrease frequency, and XCO_tune values less than approx 16 will increase frequency.
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MICRF506
To avoid this situation, always make sure max count is between limits. Suggestion: Count for 8 (or 16) bits only. Procedure description: In the procedure below, UP+DWN pulses are counted, and only the sign of the FEE is used. The value of n is 8 or 16. Assumption: A transmitter is sending a 1010... pattern at the correct frequency and bitrate. The wanted receiver frequency is the mid-point between the "0" and "1" frequencies.
Input: Nothing Output The best XCO_tune value (giving the lowest IFEEI) Local variables: XCO_Present: (5-bit) holds present value in XCO_tune bits XCO_Step: (4-bit) holds increment/decrement of XCO_tune bits SCO_Sign: (1 bit) holds POS or NEG (increment/cerement) increasing LO is done by reducing the XCO_tune value XCO TUNE PROCEDURE INT: XCO_Present = 0 XCO_Step = 32 XCO_Sign = NEG Control_Word = Default RX, clocks match transmitter LOOP: XCO_Step = XCO_Step/2 XCO_Sign == POS? Yes --> XCO_Present- = XCO_Step // increase LO No --> XCO_Present+ = XCO_Step // decrease LO XCO_tune bits = CXO_Present Program RFChip
Delay > n bits Read FEE FEE > 0? Yes --> XCO_Sign = POS No --> XCO_Sing = NEG // negative or == 0 XCO_Step > 1? Yes --> Branch to LOOP No --> XCO_Sing ==POS? Yes --> XCO_Present- = 1 Branch to FIN FIN: RETURN, return-value = XCO_Present
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M9999-092904 (408) 955-1690
Micrel
MICRF506
Package Information
32-Pin MLF (B)
MICREL, INC. 2180 FORTUNE DRIVE, SAN JOSE, CA 95131 USA
TEL +1 (408) 944-0800 FAX +1 (408) 474-1000 WEB http:/www.micrel.com
The information furnished by Micrel in this data sheet is believed to be accurate and reliable. However, no responsibility is assumed by Micrel for its use. Micrel reserves the right to change circuitry and specifications at any time without notification to the customer. Micrel Products are not designed or authorized for use as components in life support appliances, devices or systems where malfunction of a product can reasonably be expected to result in personal injury. Life support devices or systems are devices or systems that (a) are intended for surgical implant into the body or (b) support or sustain life, and whose failure to perform can be reasonably expected to result in a significant injury to the user. A Purchaser's use or sale of Micrel Products for use in life support appliances, devices or systems is a Purchaser's own risk and Purchaser agrees to fully indemnify Micrel for any damages resulting from such use or sale. (c) 2004 Micrel, Incorporated.
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M9999-092904 (408) 955-1690

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